Well, good morning, it's a pleasure to be here at International Supercomputing.
For those of you I haven't had the pleasure of meeting personally, I've been at Intel
about 18 years, the last five years responsible for Intel's server workstation and storage
business, including Xeon, the Itanium processor, and our initiatives into high-performance computing.
So today, I want to celebrate our accomplishments on Petascale, but very quickly talk about
the challenges as Intel, the sponsors of tomorrow, driving to exascale class computing
by the end of the decade.
Before I start, on behalf of Intel Corporation, let me congratulate Professor Dr. Muir on
a fantastic show.
We continue to be very happy being platinum sponsors of this, and we really appreciate
getting the entire HPC community together.
Congratulations on your 25th anniversary.
So, what's ironic, perhaps, is that Intel is also celebrating its 25th anniversary
in high-performance computing.
If we go back to 1985 and the work we did with Caltech and our now Chief Technical Officer
Justin Ratner, who I think has addressed you many times here, we had the Intel first parallel
supercomputer in 1985 based on the 286 and the 287, codenamed the Cosmic Cube and generating
a 3.2 megaflops.
The Cube was this view into the future that all things could be possible with the Cosmic
Cube, and that was really the beginning of what we did in supercomputing.
So as we look since then, Intel's had a pretty rich history of accelerating our presence
in high-performance computing from the Intel 860 to the Pentium Pro, and then onwards through
multiple generations of Xeon.
When we brought the Pentium Pro to market really our first branded server microprocessor,
the marketplace was hundreds of thousands of servers.
And this year we'll sell over 15 million chips together as an industry, really based on the
economics that Moore's Law brought to servers and obviously to high-performance computing.
But at the same time, Intel has about 10% of our employees now as software developers.
So with 80,000 employees, that means we have over 8,000 software developers.
And so from the early 90s with Unix compilers to VTune performance analyzers to Linux compilers,
MPI libraries, and now threading building blocks, we have a strong commitment to the
HPC community, not just in the hardware or the chip, but also in our software.
So Moore's Law has kind of brought this economic adoption of volume economics on industry standard
hardware, and so we're happy to see on today's list that Intel is now in 408 of the top 500
computers in all time high position for us, but we're certainly not going to stand still.
And I'm going to talk to you about some significant new investments today we're making to accelerate
the road to exascale computing by the end of the decade.
And those investments will stay on the fundamental principles that got us to where we're at today,
which is volume economics, an IA programming model that simplifies the compute model.
You heard the response to the China Academy of Science that today GPGPUs are just too
hard to program, but also a robust software ecosystem, and you'll hear that from me over
the course of the discussion today.
So at the foundation of all this, of course, is Moore's Law doubling the transistors every
18 to 24 months, getting performance for serial and parallel applications, and delivering
more cores and more threads at similar to lower power levels, and this has really been
the foundation of transforming the economics of HPC.
But I think every year I get asked, can we continue on Moore's Law?
So let me give an update on where we're at.
Moore's Law is alive and well at Intel.
If we look at our 32-nanometer technology, we're ramping four factories, $7 billion of
factories over the next two years.
This is a 22-nanometer wafer.
We're actually on track for 22-nanometer in 2011 production.
So for those of you that think that Moore's Law is not alive and well at Intel, we feel
very good about it.
It's not just 22-nanometer.
What we're showing here is we've talked about this tick-tock model of having a new processor
architecture and a new process technology every other year.
We see a path well into the next decade from 22-nanometer, which we're on track for, production
wafers at the end of 2011, to 15-nanometer in 2013, to 11-nanometer in 2015, to 8-nanometer
in 2017.
We're looking at research around nanowire, optical interconnects, carbon nanotubes, all
these things.
We see a path, so there's really no end in sight to the benefits that we've had of Moore's
Law and those economics we've seen since the 2000 in timeframe.
And at the same time, we're still seeing an insatiable need for computing.
That's what excites Intel so much about this supercomputing show is that you are the ultimate
drivers of the requirements for performance.
If we look at the petascale class systems we're at today, one petaflop system for CT
cancer detection takes about six minutes.
That's an improvement from a 50 teraflop system that took two and a half hours to compute
a CT scan.
So we've gone already from two and a half hours to six minutes.
As we look to 10 petaflops, we'll be able to get that down to less than a minute.
So as we're doing full MRI, CT scans, this is a mission-critical thing for patients.
They can get real-time and immediate results.
If we look at genomics and less than 100 teraflops, we can really, really only model a small part
of a cell.
If we look at an exaflop of computing, we're talking about modeling an entire cell and
ultimately getting to genomics or custom pharmaceuticals that are custom to a certain person's gene
pool or race.
And then when we talk to NASA, they're talking about a zettaflop of computing or a million
times what the entire top 500 list is that you showed to today to do global climate simulation
and long-range weather forecasting.
So we are very much excited about getting to a petascale on the list today, but we're
very much setting our sights now on exascale and ultimately zettascale.
So I talked about the process that is every two years until we'll be coming out with a
new manufacturing process.
At the same time, we've been very consistent on our strategy of how we deliver more performance
to you and lower power, maybe more importantly, on each and every year in generation.
So we've called this TikTok for 2005, since 2005, and actually it's almost gotten kind
of boring maybe because it's become so predictable.
But the good news is there's no end in sight.
Every year you will get either a new microprocessor design and then the alternate years are on
the tick years, you will get a new process technology.
So what I'm showing you basically is a roadmap out as we ramp Westmere or the Intel 5600
this year on 32 nanometer, a new microarchitecture coming approximately a year away on Sandy
Bridge, a new 22 nanometer compaction of that onto Ivy Bridge, and then a new talk out beyond
that.
And each and every time we do that, we're adding new instructions, more so instructions
that will be useful to you in the HPC community, as I'll talk about a second on AVX instructions.
So this TikTok is really the foundation of how we'll deliver performance in the volume
of the marketplace.
Now one area that we got a lot of feedback on over the last several years from you as
an audience is we were not participating in fat node clusters.
And we were very successful in two socket and one socket machines, but not in the four
and eight socket machines.
So the product we just launched this quarter, or the last quarter actually, the Xeon 7500
is now the largest leap in performance in the history of us being in the server business.
About 40% of the installed base and servers in the world are on that Xeon 3.33 gigahertz,
40%.
And in the same power envelope, in the same data center, if you just replace that 40%
of the installed base, you can now get 20 times the performance in the same power and
thermal envelope.
It's just a few years ago today.
So this is our first eight core symmetric multithreaded machine.
And we're starting to enter high performance computing space because we've gotten eight
times the memory bandwidth and obviously a significantly more course.
We're delivering a much more balanced machine.
So what I thought I'd do is I introduce Jean-Philippe Nomine, who is the HPC division's lead at
CEA Dam.
And he is here in place of Jean Guinard, who could not travel, unfortunately, today.
So Jean-Philippe, thank you for coming.
Thank you, Kirk.
So maybe you can tell us a little bit about what you're doing at CEA as well as the Xeon
7500.
Yeah.
Thank you, Kirk.
Good morning, everybody.
I'm very pleased to be here today to introduce you our brand new supercomputer at CEA.
So I work with the Terra 100 project team and Jean Guinard at CEA, and I'm also involved
in European HPC throughput project.
But today, our point, our topic is Terra 100.
We have just powered on, and as it has been powered on ahead of schedule, we took this
opportunity to present you this new machine, which we consider a very significant industrial
success for us between CEA, Intel, and Bull Company.
So in a few words, Terra 100 is a machine of world records.
It's a 1.25-petaflops peak performance machine made of 4,300 nodes, 140,000 cores, Intel
Xeon 1700 series.
It has a quad data rate in feedback interconnect.
It has an open source software stack.
It has 300 terabytes of memory, 20-petabytes of DIX storage with a luster fire system,
and 500 gigabyte, gigabit, sorry, per second bandwidth to the global fire system.
But besides the records I mentioned, our point is really that Terra 100 is a production machine
with a very high reliability, and it's designed for strategic needs of CEA.
And let me elaborate quickly a little bit on this.
Because Terra 100 is also for us a step on our more general roadmap.
If you take CEA scientific and technical activities, they span a very broad range of domains beyond
defense and security to which Terra 100 is dedicated.
It goes beyond this, including but not limited to climate change, energy, earth, and universal
sciences, life sciences.
So CEA is a major player in HPC because numerical simulation is an essential tool for these
application domains.
And we have a global vision of the corresponding computing resources and services around the
computers and of the evolution of these resources and services with an open and a classified
supercomputing center which are complementary to each other.
We've been operating this dual system of an open and a classified computing center
from 2003 onward with CCRT, and we are going to add to that fairly soon also a praise to
the omission to our systems on the open side for research.
So for us, this is part of an ambitious roadmap which has a strategic goal, which is clearly
maintaining the capacity of designing and building very large computing systems in
Europe.
And we at CEA Adam have the operational responsibility of implementing this roadmap.
So to finish with that, CEA would like to thank Intel and with a very, very special
mention to Richard Brackett.
Thanks for delivering us on schedule all the NLM chips.
Thanks for giving us the opportunity to present the machine today.
The last world, please join us tomorrow at 1 p.m. at Bulboof, free to hold for a drink.
Dr. Gunnar had to postpone his arrival at ESIC today, he was very upset about this,
but we expect him tomorrow morning and he will be very happy to share his vision with
you at this occasion.
Meet us, we will begin to prepare the future of Europe and HPC with you.
Thank you very much.
So I think it's a great example now, over a quarter million threads operating on a 1.2
petaflop machine.
So that's just the beginning, what we're rolling out now.
Of course, we're talking today about the future with you and the next talk is Sandy Bridge.
Sandy Bridge, I think, is going to be outstanding for the HPC community.
It's on track.
It will deliver significantly higher performance through higher core counts, hyperthreading
technology and something now that you can look in several papers on around new advanced
vector extensions and these advanced vector extensions in the processor will deliver up
to two times the flops per clock peak.
And this is really the beginning, and I want to make sure I say this very clearly.
This is the beginning of a new commitment from Intel to significantly accelerate the
floating point in our core Xeon roadmap.
If you look historically over the last several years, we think we've been doing a good job
on floating point, but HPC is now 25% of the server business at Intel, and we're going
to start doing more and more in the processor cores to cater specifically the Xeon processor
specifically for HPC.
So we've talked about AVX, it's public, it doubles the flops per clock peak, we've talked
about a roadmap that will add, fuse, multiply, add, and I can tell you there's a roadmap
beyond that will put us on a different trajectory, a much faster trajectory on floating point
performance on the core product line.
Okay.
So that's sort of a quick snapshot at the roadmap, but as we look forward, I think what
we are interested in is bringing pedoscale to the masses and getting to exascale.
I think we're all very well aware of the programming challenges, as was just mentioned with the
speaker ahead of me, where we're seeing irregular patterns and data structures, scaling the
multi-core as hard as we put more and more cores into Xeon, it becomes even harder, we
have new vector instructions, et cetera.
So it is a big challenge that we have up against us on pedoscale programming.
So at the same time, the programming model of the Intel architecture CPUs has been very
flexible.
If we look at instruction parallelism, data parallelism, thread parallelism, cluster parallelism,
we've been working very, very hard on the software tools to be able to address this
serial node-level performance optimization with our compiler optimizers, with our libraries,
as we look at things like parallel and node-level optimizations with things like OpenMP support,
and now with multi-node and cluster-level support around MPI Checker, really the beauty
of x86 or Intel architecture and the software tools has been this ease of programming.
And of course, over 75% of you, I think, today are using this set of software tools, whether
it be the advanced parallelism tools, the compilers, the libraries, the thread checkers,
the VTune toolkits, and now this parallel studio to really bring it to the masses outside
of just HPC and to consumer to get multi-core and multi-threading done as well.
So we have a very strong commitment within our tools chain to maintain your code investment
that you're investing so heavily in.
At the same time, we're out educating the world so that the people that come into your
labs and into your businesses over the next several years are going to have a core competency
around this parallel programming.
And just in the last couple of years now, we've trained over 2,000 universities in 88
years, 4,000 faculty and professors, and 320,000 students.
So if you're not familiar with this multi-threading parallelism courseware, please go to Intel.com
think parallel and we can get your universities or your labs in the program.
This is a significant commitment to us to get the next generation of programmers coming
out of school with an awareness around parallel programming.
Okay, so that kind of talks about petascale to the masses.
What do we think about exascale?
Well certainly we want to get to exascale by the end of the decade.
We know the challenges around power and energy per operation on the computation, on the fabric,
on the memory.
We know about taking hundreds of thousands of threads that we just saw from CEA with
280,000 threads and now looking at millions and even billions of threads.
We know there's a storage capacity and bandwidth issue.
We know that managing these high count node systems in the existence of failures or mean
time between failures is going to be a challenge.
And then last but not least, how are we going to make this affordable?
So this is the commitment that Intel has of trying to solve these challenges as we go
from petascale to 100 petaflop to an exaflop of computing by the end of the decade.
So today, Intel is announcing a new exascale lab.
In November, we launched an ExaTec lab in Paris where we were focused on the performance
and scalability of exascale applications.
And today, with Uliq and ParTech, we're announcing an exascale cluster and scalability reliability
lab.
That's showing our commitment to Europe, showing our commitment to exascale and to showing
that we're working with the industry to help solve some of these challenges that I talked
about on the last page.
So what I want to do now is bring up Dr. Pradeep Dubey, who's a senior principal engineer
at Intel and who is the director of our throughput computing lab.
Pradeep's been working in throughput computing and highly parallel workloads for over two
decades, first at IBM and now at Intel.
So Pradeep, thanks and welcome.
So Pradeep, you know, exascale is hard, right?
We're just getting to a petaflop.
Tell me a little bit about what you've been doing at Intel Research on many core computing.
So Kirk, over the last almost a decade, we have been trying to understand the needs of
these applications.
So these applications were introduced in 2004 as RMS applications, recognition mining synthesis
at RIDF.
And they basically are a class of, a broad class of problems.
They include HPC, financial analytics, seismic processing and data visualization.
They also include throughput apps such as web mining.
They also include digital content creation apps such as volume rendering, engineering
design, type apps.
In each case, we have been working with a leading industry co-traveller such as Mayo
and CERN.
We have been working with a leading academic researcher such as Professor FedQ at Stanford
and trying to understand what if we are actually designing a processor just for that one application
or just for that one customer.
In that exercise, we get to understand what's, if anything, we need to do different for the
need for that, for that specific need of that application or customer.
It's a win-win situation.
The co-traveller also benefits by future-proofing their algorithmic thinking, their algorithmic
choices so that they can scale nicely on this class of problems for all the systems that
we're building.
So you're working with the industry.
You're looking at these select, very highly parallel workloads.
And what are you seeing in terms of the parallelism on those workloads?
Oh, very encouraging results.
You'll see what we have discovered is that for these problems, this large amount of parallelism.
And they nicely scale, even with the limitations that we are talking about, the scaling is
pretty good, very encouraging.
The key attribute for these problems is that there is high enough parallelism.
Parallelism almost high enough to the point that you can make a very fundamental tradeoff.
This tradeoff was observed by head of our lab then in 1999, almost a decade back, Dr.
Fred Pollack.
He made this very simple observation that if you have enough parallelism for that class
of problem, you can actually tradeoff the single-thread performance and offer even higher
compute density.
And two cores will therefore do better than one core using up the same transistor budget.
So that is the key in this sense for these problems, and only for this class of problems
for offering even higher performance than we have been so far.
So you've been looking at these highly parallel workloads for almost two decades now, or working
on it over two decades.
You've been doing some research chips as well.
So why don't we talk about the research chips?
Sure.
So we have been there for prototyping research chips.
One was our first 80-core processor.
80?
80 core, yes, in 2007.
First teraflop delivered for less than 100 watt.
That was in 2007, our Polaris chip.
And recently, we did a single-chip cloud computer, 48 core, primarily meant for looking at programming
model challenges, right, for clouds.
And that, again, has been very encouraging response from the academia and industry for
the cloud chip.
Additionally, we have been publishing extensively.
So we have, and demonstrating.
So at the last supercomputing, and close to six months back, Justin Ratner, our CTO, demonstrated
the first sustained dense matrix multiplied teraflop single chip on the Laraby processor.
And soon after, and additionally, talking about publications, we have published fastest
relational join, fastest search, fastest sort, fastest LU coming up soon.
So all of these are leading the best that you can find highest performance publications.
And especially note two upcoming ones.
We have one publication coming up at ISCA architecture conference in France.
And that is about debunking the 100x CPU-GPU myth.
The second paper is on fastest research at SIGMOD in Indianapolis.
Next month, actually this month, June 6th to 11th.
And that paper has been judged as the best 2010 paper by SIGMOD that we just told a couple
of days back.
It's on research.
And again, that paper has data from CPU, GP, as well as night's fairytale across the board.
So since 1999, all of these highly parallel papers, three research chips, the 80 core,
the Laraby that we've talked about at supercomputing 09 with Justin, and the single-chip cloud
computer, the 48 core single-chip on a cloud computer chip.
So what is the takeaway from all this after your research?
That's a very good question.
In summary, our findings suggest that there is no shortcut to building a general purpose
parallel processor.
So if you look at the needs of these parallel applications, there needs a fairly general
purpose.
Meaning, first of all, you cannot ignore the single-thread performance.
You have to find that right balance between single-thread performance and parallel performance.
And when it comes to parallel performance, again, you don't put a label on that parallelism.
You have to support the various forms of parallelism, data, thread, task, process.
And when you offer that balance support for parallelism, you have that balance architecture
which magically addresses the big challenge that we are facing, which is the program or
productivity improves significantly.
And that is really the key finding so far for us, the balance approach to architecture.
Well, hey, at the end of the day, I'm a product guy.
I deliver products to everyone here.
I think one of the great things about Intel is taking research into production.
And so after 10 years of research, I want to introduce with Pradeep a new architecture,
probably the most fundamental architecture change since the Xeon processor, and we'll
do that right now.
So what Intel is introducing today worldwide is the Intel Many Integrated Core Architecture.
This is the newest addition to the Intel Server product family.
It's a co-processor architecture.
It's delivering on many Intel cores, all Intel architecture-compatible cores.
And it will deliver a heterogeneous set of software tools to the marketplace, consistent
with the tools being used today for multithreading and multiprocessor systems.
This chip will be dedicated to highly parallel applications, as we just talked about.
And again, it will greatly simplify the software programmability that we talked about in traditional
accelerator architectures.
So let me go into a little bit more detail on what we mean by this Intel Many Core Roadmap
before I drop that wafer.
So Pradeep, why don't we talk a little bit about what we mean by Many Integrated Core
Architecture, OK?
So Kirk, the key attributes of this architecture are, first, that general-purpose core.
That's at the heart of it, the x86 core.
It's been extended with a vector unit, 512-bit SIMD, vector unit which has a very important
feature called Gather.
So it's a very good support for Gather operations, critical to HPC apps, very high bandwidth
on-die interconnect, and a large coherent shared L2 cache.
And that simplifies the programming challenge.
So the key attributes, again, large core count, high memory bandwidth, high interconnect bandwidth,
as well as supports like Gather.
Five 12-bit SIMD as well.
Five 12-bit SIMD.
OK, great.
So let's talk a little bit more about what we would deliver that would make this a reality
to you.
So what we're announcing today is a new software development vehicle program.
We alluded to this at Supercomputing 09 with Justin.
But what we're going to be delivering is coprocessor solutions, Intel architecture core-based.
The first software development vehicle will be called Knight's Ferry.
We're putting over 100 new instructions into the Intel architecture instruction set dedicated
to these coprocessing capabilities.
This software development platform, which will ship in a Xeon system with these PCI
Express cards in them, will be available from Intel so you can contact your Intel representatives.
The first instantiation of the SDV will be 32 cores.
Each core will be four threads per core, so 128 threads of computing in this machine,
8 MEG shared cache, and it will fit in a standard PCIe thermal envelope.
So the big news here is that we'll have these bundled with Intel HPC tools that I'll talk
about in a second, that because there's Intel architecture cores both in the PCIe coprocessor
as well as in the Xeon sockets, we'll be able to optimize for the big cores as well
as the small cores, everything being Intel architecture based.
So with that, why don't we take a look at what we think this product can do.
And with that, let me talk about the software programming.
So probably the most fundamental part of this announcement is the programming model.
You just heard from the speaker before me the complications of programming to a GPGPU.
Well again, today we're taking the same software tools, compilers, math kernel libraries, all
of the Intel software tools that you've been using as an industry for over a decade, and
we're now going to expand them into a heterogeneous set of tools that will be able to optimize
your code to the CPU cores that are in the Xeon sockets as well as to the IA Intel cores
that are in the PCI Express sockets.
So again, the compilers, the development tools and libraries, all the coding methodologies,
you do not need to learn a new programming language.
You can use the same languages that we've had around C, C++, Fortran, compilers, et cetera.
So what we're showing on the chart here is as we go to more and more cores on Xeon,
we've already gone from four to eight and beyond, you can get the same optimization
across these tools on the Intel architecture cores that are in the CPU sockets, but as
we go, as you see on the right side, we go to big cores in Xeon and small inter-architecture
cores in the PCI Express Knights family cards, you'll be able to optimize those seamlessly
if you have these coprocessors installed into the system.
And over time, as we've talked about all these research chips, you should rest assured that
Intel is looking at all these different combinations.
Big cores in one socket, small cores in another.
Big and small cores in the same socket.
Big cores in Xeon, PCI Express cores in the other.
The benefit to you is the software programming model should be seamless.
You continue to reuse the Intel software tools and you don't need to spend a year learning
any other programming language.
So with that, why don't we show you a demonstration of the capabilities of this first software
development vehicle.
So Pradeep, what do we have here?
It looks like we have an SDV system, and this is just a standard SDV workstation, and inside
is the Knights Ferry first SDV platform card that we talked about.
Tell us a little bit about what we're going to run on this.
So what we're doing here is we're running LU, which is a LU decomposition, like matrix
decomposing into lower and upper triangular matrices, very important operation.
And what we've done is just with a fraction of compute power of Knights Ferry, we're already
better than the best published number on LU.
And if you unleash all cores and threads, you see the performance will go up, and in
fact, it will go up to achieving a milestone of half a teraflop.
So we have a portion of the cores running on the card.
The best published number is around 400 gigaflops per second on any architecture out there, GBGPU,
Xeon, AMD, et cetera.
And as we work on this LU performance number, we're bumping up, and now we're over 500 gigaflops
per second.
One of the things we did to the software team is I challenged them as they built this
demo to spend no more than three hours optimizing the code.
So everything you're seeing here is almost out of the box, taking the Intel tools, and
with less than three hours of optimization time, getting a world record gigaflop per
second on any architecture on a coprocessor.
We think there's a lot of headroom, I think, still left to be had on this.
Is that true?
If you go by the efficiency numbers we have on our multicore, you can clearly see there
is a lot more room here to improve performance.
And it's nowhere near.
That's fantastic.
So let's summarize, if we could, then what was that interesting or not interesting?
Okay, so let's summarize quickly what we showed at Supercomputing 09 in Portland, and then
what we're showing six months later, if you could, for the audience.
So we then showed how you can achieve a teraflop sustain for dense matrix multiply, and also
leading performance on sparse matrix vector multiply.
And now we are showing that we can also achieve the highest published performance on LU decomposition,
which is the method of choice for Linpak.
Okay.
Very good.
Thank you very much, Pradeep.
Thank you.
Thanks for all your great research.
We're happy to bring it to a product.
So what we're talking about today is a multi-hundred-million-dollar commitment to you, the HPC community,
as we significantly increase research not just in Xeon and Itanium, but also in these
Intel architecture-based coprocessor solutions.
So what else do we want to announce today?
Well, this is just the beginning.
The Knights Ferry software development platform with 32 cores is already setting world records.
The first product that we'll bring to marketplace is actually going to be accelerated directly
onto our 22-nanometer technology.
And we'll have more than 50 Intel architecture cores.
And we're quite confident this will be the highest compute platform in the world when
combined with Xeon.
Again, you'll have heterogeneous tools that we'll be able to optimize.
So all the good work you're doing today on Intel tools for the multi-core processing
will be seamless onto the Knights Ferry and Knights Corner and the Xeon processors.
And then we'll have a family of products beyond that that you'll have a good reason to come
back to international supercomputing on to hear the future of this Knights product roadmap.
So SDV platform today, 22-nanometer product with more than 50 cores on this Knights coprocessor.
Okay, so the good news is we've already started shipping this software development vehicle
to some of our end-user customers.
So what I wanted to do now is not just have you hear it from Intel, but understand how
this is being used in real time in some end-user applications.
So I'd like to introduce Sver Yarp, Chief Technical Officer of CERN Open Lab, to talk
about their experiences.
Sver, thanks for joining.
Hi there.
So, obviously, we've had a long relationship.
Tell me a little bit about what's going on at CERN.
Yeah, so we're up and running with the Large Hadron Collider, so this is very exciting
for us.
We have record beam energy, so we have some problems initially.
It is not so unexpected since this is A0 stepping of a very complex accelerator, but by now
we've achieved billions of recorded events, and there are four cathedral-like detectors
that are now being used to record, and later on the physicists on these experiments will
analyze and hopefully detect new physics.
Okay, so how about the compute capacity behind this thing?
Yeah, so we heard a lot about systems with about 200,000 cores being close to the top
of the top 500 list.
We have a distributed computer system, so this is a grid, probably the largest grid
operating in the world, and it represents 200,000 cores, as I just said, and probably
20% of that is installed at CERN.
So it's a pretty large and complex installation.
What I should also mention is that, of course, when I say 200,000 cores, this is what we
can afford right now.
When we ran the previous accelerator in the 90s, we increased the performance of our center
by three orders of magnitude as we went from the beginning of the LEP accelerator to the
end.
So we're hoping that this time we can do the same.
That's great.
So what I'm showing on this slide is the fact that we have four main domains of computing
at CERN.
We have, in the top left-hand corner, the online trigger, so since the beams run into
each other at 40 megahertz, there's no way we can record all of that data.
So we have to trigger and select the most interesting physics events at the online,
but then later on we can do an offline reconstruction, which is a more careful reconstruction.
So we really have enough time to consider the details of the physics quite carefully.
But what interests the physicists is to do individual analysis.
So this is often where they sit in front of a workstation and look at thousands or maybe
millions of events to find new physics via statistical methods.
And all of this is compared with simulation already from CEA.
We heard the importance of doing careful simulation, and we are no different.
We do careful simulation of the physics.
So this is sort of the four key areas of computing that we indulge in.
So we recently sent you one of these Knights Ferry software development platforms, and
I talked about some of the benefits.
What have you seen at CERN now?
Well, what we can confirm is definitely that porting is very, very easy because you do
find this familiar environment of bringing the code over and just recompiling.
And in a very short period of time, so in our case, probably a couple of days, we had
the first benchmark up and running.
So just a couple of days.
A couple of days.
And very satisfactory results because this was from the high-level trigger areas.
We were able to use the essential features that you described in this new architecture,
both with the vectors and with the multiple threads and the cores.
Just within a couple of days, you brought the code in.
Given it was Intel architecture compatible, you had it running almost unoptimized faster
than anything you had seen from Intel or anyone else in the industry.
Very impressive performance, again, given the features of this new architecture.
So we're now very, very keen to port the other benchmarks we have.
And we're particularly optimistic about, for instance, areas like the data analysis,
because if we can accelerate the work of the individual physicists who are actually sitting
there waiting for the results, we think that can be a great achievement and can help us
accelerate getting to interesting physics results as fast as possible.
That's fantastic.
Thanks for a great collaboration.
Okay.
Thank you, Kirk.
We look forward to shipping you a bunch of nice fairies.
Okay.
We're waiting impatiently.
Thanks again.
Thank you.
So let me try to summarize what we've talked about in the last 40 minutes.
First and foremost, Moore's law is alive and well.
We have a path from today's 32 nanometer.
You saw the health of 22 nanometer onto 15 and all the way to 8 nanometer with our research.
We see no end in sight.
We're talking about a fundamental different trajectory on floating point, which I think
is important that it's with the standard Xeon product will represent still the vast
majority of what we do together as an HPC community is in the standard roadmap.
And we're committed to accelerating a floating point with Sandy Bridge coming with advanced
vector extensions and beyond.
And then as we look forward to Pettisflop and ExaFlop class computing, we've announced
a new Exascale lab here in Europe with Uliq and ParTech.
We're announcing a new Intel many integrated core architecture today.
We're announcing a commitment for HPC heterogeneous tools.
So all the good work you've done on the multithreading and multiprocessing to date on Xeon will
be seamless to these new coprocessor solutions.
And we'll have a nice family of coprocessors that are dedicated to these very highly specialized
parallel applications that are very important to HPC.
And we'll have a first 22 nanometer product out with more than 50 cores and an SDV platform
ramping through 2010 and 2011 software development platform for you to begin working on this
called Knights Ferry with 32 cores, rather.
So hopefully that's a great story for us both, and we really, really look forward to another
decade of fantastic performance together.
Thank you very much.